Transaction response modification within interconnect circuitry
US9892072B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Oct 5, 2015 |
| Grant date | Feb 13, 2018 |
| Priority date | — |
| Expiry date | Apr 15, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4282
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Interconnect circuitry for connecting transaction masters to transaction slaves includes response modification circuitry. The response modification circuitry includes shortlist buffer circuitry storing identification for modification target transaction responses. The response modification circuitry uses this identification data to identify among a stream of transaction responses in transit a modification target transaction response. The response modification circuitry then serves to form a modified transaction response to be sent in place of the modification target transaction response to the transaction master.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.