Patent · US Active

Methods and apparatuses for command shifter reduction

US9892770B2 · kind B2 · utility

3Cited by
2References
23Claims
0Family size

Assignee

Inventors

Key dates

Filing dateApr 22, 2015
Grant dateFeb 13, 2018
Priority date—
Expiry dateApr 22, 2035

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG11C2207/2272
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.