Memory controller with dynamic core-transfer latency
US9892771B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2015 |
| Grant date | Feb 13, 2018 |
| Priority date | — |
| Expiry date | Mar 24, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory controller having a controller core and a physical signaling interface, the controller core outputs a request for read data to the physical signaling interface specifying one of at least two memory components from which the read data is to be retrieved. In response to the request for read data, the physical signaling interface outputs a memory read request to the specified memory component, receives the read data from the specified memory component, and transfers the read data to the controller core at either a first time or a second time according to whether the specified memory component is a first memory component or second memory component of the at least two memory components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.