Content addressable memory with match hit quality indication
US9892789B1 · kind B1 · utility
2Cited by
6References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2017 |
| Grant date | Feb 13, 2018 |
| Priority date | — |
| Expiry date | Jan 16, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A logic circuit is provided including at least two input cells and a sense circuit. The input cells are connected to a common result line. Further, the input cells are operable for influencing an electrical quantity at the result line. The sense circuit is connected to the result line, and is adapted to output a discrete value out of more than two possible values based on the electrical quantity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.