Cache management request fusing
US9892803B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 26, 2014 |
| Grant date | Feb 13, 2018 |
| Priority date | — |
| Expiry date | May 21, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6042
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a plurality of processing cores and a cache memory shared by the plurality of processing cores. The cache memory comprises a size engine that receives a respective request from each of the plurality of processing cores to perform an operation associated with the cache memory. The size engine fuses the respective requests from two or more of the plurality of processing cores into a fused request. To perform the fused request the size engine performs a single instance of the operation and notifies each of the two or more of the plurality of processing cores that its respective request has been completed when the single instance of the operation is complete.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.