Method of manufacturing stacked nanowire MOS transistor

US9892912B2 · kind B2 · utility

Assignee

• INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES · CN

Inventors

• Huaxiang Yin · Beijing, CN
• Changliang Qin · Beijing, CN
• Zuozhen Fu · Beijing, CN
• Xiaolong Ma · Beijing, CN
• Dapeng Chen · Beijing, CN

Key dates

• Filing date: Apr 16, 2015
• Grant date: Feb 13, 2018
• Expiry date: Apr 16, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D99/00
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods of manufacturing stacked nanowires MOS transistors are disclosed. In one aspect, the method includes forming a plurality of fins along a first direction on a substrate. The method also includes forming stack of nanowires constituted of a plurality of nanowires in each of the fins. The method also includes forming a gate stack along a second direction in the stack of nanowires, the gate stack surrounding the stack of nanowires. The method also includes forming source/drain regions at both sides of the gate stack, the nanowires between the respective source/drain regions constituting a channel region. A stack of nanowires may be formed by a plurality of etching back, laterally etching a trench and filling the trench. The laterally etching process includes isotropic dry etching having an internally tangent and lateral etching, and a wet etching which selectively etches along respective crystallographic directions.