Hard mask composition, carbon nanotube layer structure, pattern forming method, and manufacturing method of semiconductor device
US9892915B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2016 |
| Grant date | Feb 13, 2018 |
| Priority date | — |
| Expiry date | Oct 5, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K85/221
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method of a semiconductor device includes forming a hard mask layer on a semiconductor substrate using a hard mask composition. Hard mask patterns are formed by patterning the hard mask layer. Semiconductor patterns are formed by etching the semiconductor substrate using the hard mask patterns. The hard mask composition includes a plurality of first carbon nanotubes (CNTs) having a first length, a plurality of second CNTs having a second length, which is at least 3 times the first length, and a dispersing agent in which the first CNTs and the second CNTs are dispersed. The total mass of the first CNTs is 1 to 2.5 times the total mass of the second CNTs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.