Packaged wafer manufacturing method and device chip manufacturing method
US9892986B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2017 |
| Grant date | Feb 13, 2018 |
| Priority date | — |
| Expiry date | Apr 7, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a packaged wafer manufacturing method including the steps of forming a groove along each division line on the front side of a wafer, each groove having a depth greater than the finished thickness of the wafer, next removing a chamfered portion from the outer circumference of the wafer to thereby form a step portion having a depth greater than the depth of each groove, next setting a die of a molding apparatus on the bottom surface of the step portion of the wafer in the condition where a space is defined between the die and the wafer, and next filling a mold resin into this space. Accordingly, the device area of the wafer is covered with the mold resin and each groove of the wafer is filled with the mold resin to thereby obtain a packaged wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.