Semiconductor memory device
US9893271B2 · kind B2 · utility
1Cited by
7References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2016 |
| Grant date | Feb 13, 2018 |
| Priority date | — |
| Expiry date | Jul 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/01
Abstract
A semiconductor memory device includes a selection transistor on a semiconductor substrate, a lower contact plug connected to a drain region of the selection transistor, and a magnetic tunnel junction pattern on the lower contact plug, the magnetic tunnel junction pattern including a bottom electrode in contact with the lower contact plug, the bottom electrode being an amorphous tantalum nitride layer, a top electrode on the bottom electrode, first and second magnetic layers between the top and bottom electrodes, and a tunnel barrier layer between the first and second magnetic layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.