ESD protection circuit with false triggering prevention
US9893518B2 · kind B2 · utility
1Cited by
8References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 16, 2015 |
| Grant date | Feb 13, 2018 |
| Priority date | — |
| Expiry date | Jun 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H1/04
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An ESD protection circuit used to protect a protected circuit coupled between a first node and a second node against an ESD event. The ESD protection circuit has a discharging circuit and a control circuit. The discharging circuit selectively provides a current path for discharging a current from the first node to the second node. The control circuit controls the discharging circuit to switch on the current path during an ESD event. The control circuit further controls the discharging circuit to switch off the current path during the normal operation of the protected circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.