Bit-matrix multiplication using explicit register
US9898251B2 · kind B2 · utility
1Cited by
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7Claims
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Key dates
| Filing date | May 19, 2015 |
| Grant date | Feb 20, 2018 |
| Priority date | — |
| Expiry date | Dec 15, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a processor comprising, in its instruction set, a bit matrix multiplication instruction (sbmm) having a first double precision operand (A) representing a first matrix to multiply, a second operand (B) explicitly designating any two single precision registers whose joint contents represent a second matrix to multiply, and a destination parameter (C) explicitly designating any two single precision registers for jointly containing a matrix representing the result of the multiplication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.