Semiconductor layout structure and designing method thereof
US9898569B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2015 |
| Grant date | Feb 20, 2018 |
| Priority date | — |
| Expiry date | Sep 14, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for designing a semiconductor layout structure includes following steps. A first active feature group including at least a first active feature is received, and the first active feature includes a first channel length. A pair of first dummy features is introduced to form a first cell pattern. The first dummy features include a first dummy width. A first spacing width is defined between the first active feature group and one of the first dummy features and a third spacing width is defined between the first active feature group and the other first dummy feature. The first cell pattern includes a first cell width and a first poly pitch, and the first cell width is a multiple of the first pitch. The receiving of the first active feature group and the introducing of the first dummy features are performed in by at least a computer-aided design tool.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.