Method of forming semiconductor packages having through package vias
US9899248B2 · kind B2 · utility
64Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 28, 2015 |
| Grant date | Feb 20, 2018 |
| Priority date | — |
| Expiry date | Jun 15, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer and protrude from the patterned layer to expose tapered sidewalls.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.