Method of forming layout design
US9899263B2 · kind B2 · utility
12Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 9, 2016 |
| Grant date | Feb 20, 2018 |
| Priority date | — |
| Expiry date | Aug 10, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/907
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The plurality of gate structure layout patterns has a predetermined pitch smaller than a spatial resolution of a predetermined lithographic technology. A first layout pattern of the set of layout patterns has a width less than twice the predetermined pitch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.