Hybrid pitch package with ultra high density interconnect capability
US9899311B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2016 |
| Grant date | Feb 20, 2018 |
| Priority date | — |
| Expiry date | Dec 6, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.