Layout structure for electrostatic discharge protection
US9899369B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2015 |
| Grant date | Feb 20, 2018 |
| Priority date | — |
| Expiry date | Sep 22, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/611
Abstract
A layout structure is provided. The layout structure includes a substrate, a gate conductive layer, a first doped region having a first conductivity, a second doped region having the first conductivity, and a third doped region having a second conductivity. The gate conductive layer is formed on the substrate. The first doped region the second doped region are formed in the substrate and located at two sides of the gate conductive layer. The third doped region is formed in the substrate and adjacent to the second doped region. The third doped region and the second doped region form a diode. The gate conductive layer, the first doped region, and the third doped region are connected to ground, and the second doped region is connected to an input/output pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.