Low power adaptive synchronizer
US9899992B1 · kind B1 · utility
3Cited by
8References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 17, 2016 |
| Grant date | Feb 20, 2018 |
| Priority date | — |
| Expiry date | Aug 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00234
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit adapts to the occurrence of metastable states. The circuit inhibits passing of the metastable state to circuits that follow, by clock gating the output stage. In order to determine whether or not to gate the clock of the output stage, two detect circuits may be used. One circuit detects metastability and another circuit detects metastability resolved to a wrong logic level. The results from one or both detector circuits are used to gate the next clock cycle if needed, waiting for the metastable situation to be resolved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.