Cut-mask patterning process for FIN-like field effect transistor (FINFET) device
US9904163B2 · kind B2 · utility
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6References
20Claims
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Key dates
| Filing date | Jan 8, 2016 |
| Grant date | Feb 27, 2018 |
| Priority date | — |
| Expiry date | Jun 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a mask for use in a lithography system having a defined resolution. The mask comprises first and second patterns that are greater than the defined resolution and a sub-resolution feature that is less than the defined resolution. Portions of the first and second patterns are positioned close to each other and separated by the sub-resolution feature in an intersection area. The size and shape of the sub-resolution feature are such that when the mask is used in the lithography system, a resulting pattern includes the first and second patterns interconnected with each other through the interconnection area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.