High performance shifter circuit
US9904511B2 · kind B2 · utility
0Cited by
8References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2015 |
| Grant date | Feb 27, 2018 |
| Priority date | — |
| Expiry date | Dec 8, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/015
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved shifter design for high-speed data processors is described. The shifter may include a first stage, in which the input bits are shifted by increments of N bits where N>1, followed by a second stage, in which all bits are shifted by a residual amount. A pre-shift may be removed from an input to the shifter and replaced by a shift adder at the second stage to further increase the speed of the shifter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.