Multicore bus architecture with non-blocking high performance transaction credit system
US9904645B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2014 |
| Grant date | Feb 27, 2018 |
| Priority date | — |
| Expiry date | Nov 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.