Method for analyzing interconnect process variation
US9904743B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2015 |
| Grant date | Feb 27, 2018 |
| Priority date | — |
| Expiry date | Mar 19, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a corresponding system for analyzing process variation and parasitic resistance-capacitance (RC) elements in an interconnect structure of an integrated circuit (IC) are provided. First descriptions of parasitic RC elements in an interconnect structure of an IC are generated. The first descriptions describe the parasitic RC elements respectively at a typical process corner and a peripheral process corner. Sensitivity values are generated at the peripheral process corner from the first descriptions. The sensitivity values respectively quantify how sensitive the parasitic RC elements are to process variation. The sensitivity values are combined into a second description of the parasitic RC elements that describes the parasitic RC elements as a function of a process variation parameter. Simulation is performed on the second description by repeatedly simulating the second description with different values for the process variation parameter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.