Memory system and program operation method based on program speed information
US9905304B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 19, 2016 |
| Grant date | Feb 27, 2018 |
| Priority date | — |
| Expiry date | Jan 19, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5646
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There are provided a memory system having improved reliability and an operating method thereof. A memory system includes a semiconductor memory device including a memory cell array having a plurality of pages, and a controller for sequentially transmitting, to the semiconductor memory device, physical block addresses of pages to be programmed among the plurality of pages. In the memory system, the semiconductor memory device selects a page corresponding to each of the physical block addresses among the plurality of pages according to previously stored program speed information, and performs a program operation on the selected page.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.