Wafer level fan-out package and method for manufacturing the same
US9905436B2 · kind B2 · utility
8Cited by
0References
3Claims
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Key dates
| Filing date | Feb 25, 2016 |
| Grant date | Feb 27, 2018 |
| Priority date | — |
| Expiry date | Feb 25, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/92244
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a wafer level fan-out package includes attaching a semiconductor chip on a partial area of an IO pattern formed on one surface of a wafer, forming a first passivation layer on surfaces of the semiconductor chip and the wafer, forming an RDL (redistribution layer) that is electrically conducted with the IO pattern and the semiconductor chip, in a partial area of a top surface of the first passivation layer, and forming a second passivation layer on the top surface of the first passivation layer and a partial surface of the RDL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.