Integrated circuit stress releasing structure
US9905515B2 · kind B2 · utility
2Cited by
16References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2015 |
| Grant date | Feb 27, 2018 |
| Priority date | — |
| Expiry date | Apr 15, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides an integrated circuit (IC) package with stress releasing structure. The IC package comprises: a metal plane, a substrate, an IC chip, and an IC fill layer. The metal plane has at least one first etching line for separating the metal plane into a plurality of areas. The substrate is formed on metal layer. The IC chip is formed on the substrate, and the IC fill layer is formed around the IC chip. The at least one first etching line forms at least one half cut line in the metal plane and the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.