Method of manufacturing wafer level packaging including through encapsulation vias
US9905551B2 · kind B2 · utility
2Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2015 |
| Grant date | Feb 27, 2018 |
| Priority date | — |
| Expiry date | May 10, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a method of manufacturing a wafer level package. The method includes forming a repassivation layer that encapsulates a plurality of semiconductor chips isolated from a wafer, forming a through encapsulation via (TEV) in the repassivation layer, forming a redistribution layer electrically connected to the TEV, and forming a bump ball on the redistribution layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.