Integrated circuit including an array of logic tiles, each logic tile including a configurable switch interconnect network
US9906225B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 12, 2016 |
| Grant date | Feb 27, 2018 |
| Priority date | — |
| Expiry date | Dec 12, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprising a field programmable gate array including a plurality of logic tiles physically organized in at least one row and at least one column and wherein each logic tile (i) is electrically coupled and physically adjacent to at least one other logic tile of the plurality of logic tiles and (ii) includes (a) logic circuitry, (b) memory, and (c) a configurable switch interconnect network which is electrically coupled to the memory, wherein the configurable switch interconnect network includes a plurality of switches electrically interconnected and organized into a plurality of switch matrices and wherein the plurality of switch matrices are arranged in a plurality of stages. In one embodiment, each logic tile of the plurality of logic tiles is capable of communicating, during operation, with at least one other logic tile of the plurality of logic tiles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.