Systems and methods for cascading radar chips having a low leakage buffer

US9910133B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Hao Li · Poing, DE
• Herbert Knapp · Munich, DE

Key dates

• Filing date: Feb 25, 2015
• Grant date: Mar 6, 2018
• Expiry date: Feb 1, 2036

Classification

• Technology area (CPC G): Physics
• CPC primary: G01S13/931
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A cascaded radar sensor arrangement is disclosed. The arrangement includes a first buffer and a second buffer. The first buffer is within a first radar chip and includes a switch and is configured to mitigate a first leakage signal in the disabled mode. The second buffer is within a second radar chip and has a disabled mode. The second radar chip is cascaded with the first radar chip. A control unit is coupled to the first radar chip and the second radar chip and is configured to set the disabled mode for the first buffer.