Method and apparatus for partial cache line sparing
US9910728B2 · kind B2 · utility
2Cited by
1References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2015 |
| Grant date | Mar 6, 2018 |
| Priority date | — |
| Expiry date | Jan 31, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1064
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are an apparatus and method to store data from a cache line at locations having errors in a sparing directory. In response to a write operation having write data for locations in one of the cache lines, the write data for a location in the cache line having an error is written to an entry in a sparing directory including an address of the cache line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.