Feedback circuit at word line ends
US9911474B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2017 |
| Grant date | Mar 6, 2018 |
| Priority date | — |
| Expiry date | Mar 7, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Devices include an array of memory cells arranged in rows and columns. Wordlines are connected to the memory cells, and each of the wordlines is connected to a distinct row of the array of the memory cells. A wordline driver circuit is connected to a near end of the wordlines. The wordline driver circuit outputs a wordline select signal. Also, a feedback circuit is connected to a far end of each of the wordlines, opposite the near end of the wordlines. The feedback circuit includes first transistors (gated by the internal clock signal and the wordline select signal) electrically connecting a relatively lower voltage source to the far end of the wordlines; and second transistors (also gated by the internal clock signal and the wordline select signal) electrically connecting a relatively higher voltage source to the far end of the wordlines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.