Polygon die packaging
US9911716B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2015 |
| Grant date | Mar 6, 2018 |
| Priority date | — |
| Expiry date | Apr 5, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A lidded or lidless flip-chip package includes two or more polygon shaped dies. The polygon dies may be interconnected to a substrate or to an interposer interconnected to a substrate. The interposer may be similarly shaped with respect to the polygon die(s). For the lidless or lidded package, the package may include underfill under the polygon dies surrounding associated interconnects. For the lidded package, the package may also include thermal interface materials, seal bands, and a lid. The polygon die package reduces shear stress between the polygon die/interposer and associated underfill as compared to square or rectangular shaped die/interposer of the same area. The polygon dies further maximize the utilization of a wafer from upon which the polygon dies are fabricated. The multi polygon die package may allow for a significant reduction of the polygon die to polygon die relative to the spacing and may reduce signal interconnect time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.