Methods and apparatus to optimize instructions for execution by a processor
US9916164B2 · kind B2 · utility
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5References
21Claims
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Key dates
| Filing date | Jun 11, 2015 |
| Grant date | Mar 13, 2018 |
| Priority date | — |
| Expiry date | Jul 11, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, apparatus, systems and articles of manufacture are disclosed herein. An example apparatus includes an instruction profiler to identify a predicated block within instructions to be executed by a hardware processor. The example apparatus includes a performance monitor to access a mis-prediction statistic based on an instruction address associated with the predicated block. The example apparatus includes a region former to, in response to determining that the mis-prediction statistic is above a mis-prediction threshold, include the predicated block in a predicated region for optimization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.