Predictive multistage comparison for associative memory
US9916246B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2016 |
| Grant date | Mar 13, 2018 |
| Priority date | — |
| Expiry date | Sep 8, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system includes a shadow tag memory, which stores a plurality of entries containing coherency information for the cachelines residing at the various levels of private caches. If a cache miss occurs at a private cache, or if coherency information for a cacheline requires updating, a probe is sent to the shadow tag memory maintained at the shared cache to determine whether the requested (or affected) cacheline is stored at another private cache. The probe includes a tag which can be divided into two or more portions. To more efficiently compare the probe tag to the shadow tag entries, the comparison is performed in multiple stages based on the portions of the probe tag.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.