Patent · US Active

Generating a layout for an integrated circuit

US9916409B2 · kind B2 · utility

1Cited by

4References

10Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Andreas H. A. Arp · Nufringen, DE
Michael V. Koch · Ehningen, DE
Matthias Ringe · Lörrach, DE

Key dates

Filing date	Dec 8, 2015
Grant date	Mar 13, 2018
Priority date	—
Expiry date	May 4, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/398
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In an approach for generating a file, a computer generates a modified layout for an integrated circuit. The computer receives a draft layout for an integrated circuit. The computer identifies a resonator, wherein the resonator comprises a capacitor connected to ground and an inductor connected to a clock grid. The computer creates alternative resonator wiring of the received draft layout associated with the identified resonator. The computer generates a modified draft layout based on the created alternative resonator wiring for the integrated circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.