Patent · US Active

Reducing leakage current in a memory device

US9916904B2 · kind B2 · utility

0Cited by

14References

21Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Nan Chen · San Diego, US
Mehdi Hamidi Sani · Rancho Santa Fe, US
Ritu Chaba · San Diego, US

Key dates

Filing date	Feb 2, 2009
Grant date	Mar 13, 2018
Priority date	—
Expiry date	Mar 17, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG11C5/14
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Memory devices and methods of reducing leakage current therein are disclosed. The memory device includes a memory core array including a plurality of bitlines, and peripheral logic configured to interface with the memory core array. The memory device further includes a footswitch configured to isolate the peripheral logic from a ground voltage, and a headswitch configured to isolate a precharge current path from the plurality of bit lines of the memory core array. Leakage current within the memory device may be reduced via the isolation provided by the footswitch and the headswitch.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.