Integrated magnetic tunnel junction (MTJ) in back end of line (BEOL) interconnects
US9917137B1 · kind B1 · utility
10Cited by
14References
20Claims
0Family size
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Key dates
| Filing date | Jan 11, 2017 |
| Grant date | Mar 13, 2018 |
| Priority date | — |
| Expiry date | Jan 11, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is presented for forming a semiconductor structure. The method includes depositing a barrier layer, such as a tantalum nitride (TaN) layer, over a dielectric incorporating magnetic random access memory (MRAM) regions, forming magnetic tunnel junction (MTJ) stacks over portions of the TaN layer, patterning and encapsulating the MTJ stacks, forming spacers adjacent the MTJ stacks, and laterally etching sections of the TaN layer, after spacer formation, to form an electrode under the MTJ stacks. The electrode protects the MRAM regions. The electrode can be recessed from the spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.