Semiconductor device and manufacturing method
US9917187B2 · kind B2 · utility
1Cited by
5References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 5, 2015 |
| Grant date | Mar 13, 2018 |
| Priority date | — |
| Expiry date | May 5, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device comprising at least one active layer on a substrate and a first contact to the at least one active layer, the first contact comprising a metal in contact with the at least one active layer and a capping layer on the metal, the capping layer comprising a diffusion barrier, wherein the capping layer is patterned to form a pattern comprising regions of the contact covered by the capping layer and regions of the contact that are uncovered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.