Patent · US Active

Performing a repair operation in arrays

US9921906B2 · kind B2 · utility

0Cited by

5References

13Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Gerrit Koch · Herrenberg, DE
Martin Recktenwald · Eppelheim, DE

Key dates

Filing date	Jun 7, 2016
Grant date	Mar 20, 2018
Priority date	—
Expiry date	Jun 7, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/70
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method for performing a repair operation in a computer system using arrays having array cells includes detecting an error in an array. In response to detecting the error, error information is written to an error trap register. The error information includes error data and associated error detection information and a position in an array row. The error information is read from the error trap register and a corresponding data copy is determined and fetched in the computer system. One or more exact bit positions that caused the error are determined by comparing the error data with the corresponding data copy. The array cells which are associated with the determined one or more bit positions are disabled.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.