Multi-level paging and address translation in a network environment
US9921970B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 22, 2016 |
| Grant date | Mar 20, 2018 |
| Priority date | — |
| Expiry date | Sep 6, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An example method for facilitating multi-level paging and address translation in a network environment is provided and includes receiving a request for memory in a physical memory of a network element, associating the request with a first virtual address space, mapping a memory region located in the physical memory to a first window in the first virtual address space, the memory region being also mapped to a second window in a different, second virtual address space, remapping the first window in the first virtual address space to the second window in the second virtual address space, and responding to the request with addresses of the second window in the second virtual address space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.