Memory device ultra-deep power-down mode exit control
US9922684B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2017 |
| Grant date | Mar 20, 2018 |
| Priority date | — |
| Expiry date | Jan 18, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device operable in an ultra-deep power-down mode can include: a command user interface; a voltage regulator having an output that provides a supply voltage for a plurality of components of the memory device, where the plurality of components comprises the command user interface; a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode; the memory device being operable to enter the ultra-deep power-down mode in response to receiving a first predetermined command that causes the output of the voltage regulator to be disabled to completely power down the plurality of components during the ultra-deep power-down mode; and the memory device being operable to exit the ultra-deep power-down mode in response to receiving one of a hardware reset command sequence, a reset pin assertion, a power supply cycling, and a second predetermined command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.