Architecture for CMOS under array
US9922716B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2017 |
| Grant date | Mar 20, 2018 |
| Priority date | — |
| Expiry date | Feb 22, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for reducing the area and improving the performance of a non-volatile memory array are described. The non-volatile memory array may comprise a 3D NAND memory array that includes vertical NAND strings that are arranged orthogonal to a substrate. A vertical NAND string may include floating gate memory cell transistors or charge trap memory cell transistors. Sensing circuitry for sensing the programmed data states of memory cell transistors within the vertical NAND strings may be positioned underneath the 3D NAND memory array and connections from bit lines positioned above the 3D NAND memory array may be made using vertical connections extending though the 3D NAND memory array or through memory breaks within the 3D NAND memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.