Memory device
US9922728B2 · kind B2 · utility
5Cited by
2References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2016 |
| Grant date | Mar 20, 2018 |
| Priority date | — |
| Expiry date | Apr 14, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4062
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may include a plurality of memory cells; and an error detection unit suitable for latching first read data of one or more memory cells selected from the plurality of memory cells after refreshing the selected memory cells, in a first phase, and suitable for detecting errors of the selected memory cells before refreshing the selected memory cells, in a second phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.