Hybrid integrated semiconductor tri-gate and split dual-gate FinFET devices and method for manufacturing

US9922878B2 · kind B2 · utility

Assignee

• Semiconductor Manufacturing International (Shanghai) Corporation · CN

Inventors

• De Yuan Xiao · Shanghai, CN
• Guo Qing Chen · Boise, US
• Roger Lee · Boise, US

Key dates

• Filing date: Dec 11, 2012
• Grant date: Mar 20, 2018
• Expiry date: Jan 17, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6215

Abstract

A method for making a tri-gate FinFET and a dual-gate FinFET includes providing a semiconductor on insulator (SOI) wafer having a semiconductor layer over an insulator layer. The method further includes forming a hard mask on the semiconductor layer and patterning the hard mask to form first and second cap portions. The method also includes etching the semiconductor layer to form first and second fins using the first and second cap portions as an etch mask. The method also includes removing the second cap portion to expose the top surface of the second fin and forming a gate dielectric layer on the first and second fins. The method further includes forming a conductive layer over the gate dielectric layer, selectively etching the conductive layer to form first and second gate structures, forming an interlayer dielectric layer over the gate structures, and planarizing the interlayer dielectric layer using the first cap portion as a polish stop.