Interleaved video coding pipeline
US9924165B1 · kind B1 · utility
1Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2013 |
| Grant date | Mar 20, 2018 |
| Priority date | — |
| Expiry date | Jan 7, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/61
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a memory and a processor. The memory may be configured to store video data. The video data includes a plurality of sections of one or more pictures that can be processed independently. The processor generally includes a hardware pipeline. The hardware pipeline implements a number of stages of a video coding process, such that each stage performs an associated task in a substantially similar time on a different one of said plurality of sections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.