In-pipe error scrubbing within a processor core
US9928128B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2016 |
| Grant date | Mar 27, 2018 |
| Priority date | — |
| Expiry date | Sep 20, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A supervisory hardware device in a processor core detects a flush instruction that, when executed, flushes content of one or more general purpose registers (GPRs) within the processor core. The content of the one or more GPRs is moved to a history buffer (HB) and an instruction sequencing queue (ISQ) within the processor core, where the content includes data, an instruction tag (iTag) that identifies an instruction that generated the data, and error correction code (ECC) bits for the data. In response to receiving a restore instruction, the supervisory hardware device error checks the data in the ISQ using the ECC bits stored in the ISQ. In response to detecting an error in the data in the ISQ, the supervisory hardware device sends the data and the ECC bits from the ISQ to an ECC scrubber to generate corrected data, which is restored into the one or more GPRs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.