Semiconductor apparatus
US9928205B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2011 |
| Grant date | Mar 27, 2018 |
| Priority date | — |
| Expiry date | Sep 27, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4247
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor apparatus may include a master chip, first to nth slave chips, first to nth slave chip ID generating units, and a master chip ID generating unit. The first to nth slave chip ID generating units are disposed respectively in the first to nth slave chips and connected in series to each other. Each of the first to nth slave chip ID generating units is configured to add a predetermined code value to an mth operation code to generate an (m+1)th operation code. The master chip ID generating unit is disposed in the master chip to generate a variable first operation code in response to a select signal. Here, ‘n’ is an integer that is equal to or greater than 2, and ‘m’ is an integer that is equal to or greater than 1 and equal to or smaller than ‘n’.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.