Patent · US Active

Layout of large block synthesis blocks in integrated circuits

US9928329B2 · kind B2 · utility

3Cited by

8References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Harry Barowski · Balingen, DE
Harald D. Folberth · Böblingen, DE
Joachim Keinert · Altdorf, DE
Sourav Saha · Sherghati, IN

Key dates

Filing date	Jan 27, 2016
Grant date	Mar 27, 2018
Priority date	—
Expiry date	Jan 27, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F2115/08
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Generating a layout of an integrated circuit chip area from a description of an integrated circuit (IC). The description includes a register-transfer-level (RTL) design. The RTL design is partitioned in large blocks for synthesis of large block synthesis (LBS) blocks. The description of the IC further includes a floorplan for the IC, wherein each LBS block to be synthesized is assigned to a respective rectilinear shape in the floorplan and the rectilinear shapes do not overlap each other.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.