Semiconductor device including optimized gate stack profile
US9929250B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2016 |
| Grant date | Mar 27, 2018 |
| Priority date | — |
| Expiry date | Sep 27, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
Abstract
A semiconductor device is provided with an electrically conductive gate having an enhanced gate profile. The semiconductor device includes a semiconductor substrate that extends along a first axis to define a length and a second axis opposite the first axis to define a height. A channel region is interposed between opposing source/drain regions, and a gate stack is atop the semiconductor substrate. The gate stack includes an electrically conductive gate atop the channel region. The electrically conductive gate includes sidewalls extending between a base and an upper surface to define a gate height. A gate length of the electrically conductive gate continuously increases as the gate height increases from the base to the upper surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.