GaN FET with integrated driver and slew rate control
US9929652B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2016 |
| Grant date | Mar 27, 2018 |
| Priority date | — |
| Expiry date | Dec 8, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A power circuit is disclosed. The power circuit includes a power capacitor and a power resistor connected to the power capacitor. The power circuit also includes a power integrated circuit, including a GaN-based substrate, a power FET on the substrate, and a driver on the substrate. The driver is configured to charge a gate of the power FET using current from a power node. The power integrated circuit also includes a first power voltage regulator on the substrate, where the driver is configured to receive current from the capacitor through the resistor while the driver charges the gate of the power FET, and where the first power voltage regulator is configured to provide current to the capacitor while the driver does not charge the gate of the power FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.