Operation of a multi-slice processor implementing simultaneous two-target loads and stores
US9934033B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2016 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Jul 11, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Operation of a multi-slice processor that includes a plurality of execution slices and a load/store superslice, where the load/store superslice includes a set predict array, a first load/store slice, and a second load/store slice. Operation of such a multi-slice processor includes: receiving a two-target load instruction directed to the first load/store slice and a store instruction directed to the second load/store slice; determining a first subset of ports of the set predict array as inputs for an effective address for the two-target load instruction; determining a second subset of ports of the set predict array as inputs for an effective address for the store instruction; and generating, in dependence upon logic corresponding to the set predict array that is less than logic implementing an entire load/store slice, output for performing the two-target load instruction in parallel with generating output for performing the store instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.