Inventor · Austin, TX, US

Robert A. Cordes

28Patents
6h-index
33Co-inventors
65Inventor score

Filing activity: Mar 24, 2009 → May 4, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US8108655B2 Selecting fixed-point instructions to issue on load-store unit Physics 146 Active
US8380964B2 Processor including age tracking of issue queue instructions Physics 13 Active
US8127116B2 Dependency matrix with reduced area and power consumption Physics 10 Active
US9934033B2 Operation of a multi-slice processor implementing simultaneous two-target loads and stores Emerging Cross-Sectional Technologies 8 Active
US9940133B2 Operation of a multi-slice processor implementing simultaneous two-target loads and stores Emerging Cross-Sectional Technologies 6 Active
US10037229B2 Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions Physics 6 Active
US10042770B2 Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions Physics 6 Active
US8489863B2 Processor including age tracking of issue queue instructions Physics 3 Active
US10133576B2 Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries Physics 2 Active
US9798549B1 Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction Physics 2 Active
US10073697B2 Handling unaligned load operations in a multi-slice computer processor Physics 1 Active
US10067763B2 Handling unaligned load operations in a multi-slice computer processor Physics 1 Active
US10409598B2 Handling unaligned load operations in a multi-slice computer processor Physics 1 Active
US10496406B2 Handling unaligned load operations in a multi-slice computer processor Physics 0 Active
US11150907B2 Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries Physics 0 Active
US11520704B1 Writing store data of multiple store operations into a cache line in a single cycle Physics 0 Active
US11734010B2 Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries Physics 0 Active
US10223266B2 Extended store forwarding for store misses without cache allocate Physics 0 Active
US10831481B2 Handling unaligned load operations in a multi-slice computer processor Physics 0 Active
US11243773B1 Area and power efficient mechanism to wakeup store-dependent loads according to store drain merges Physics 0 Active
US12061909B2 Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries Physics 0 Active
US10169046B2 Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction Physics 0 Active
US10255107B2 Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions Physics 0 Active
US10884742B2 Handling unaligned load operations in a multi-slice computer processor Physics 0 Active
US11379241B2 Handling oversize store to load forwarding in a processor Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.